`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yu Zihao 
// 
// Create Date: 2021/08/02 13:09:36
// Design Name: 
// Module Name: datapath_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
//    At a minimum your datapath_tb should test at least the sequence shown below:
//        MOV R0, #7 ; this means, take the absolute number 7 and store it in R0
//        MOV R1, #2 ; this means, take the absolute number 2 and store it in R1
//        ADD R2, R1, R0, LSL#1 ; this means R2 = R1 + (R0 shifted left by 1) = 2+14=16
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module datapath_tb();
  reg [15:0] datapath_in,sximm5,sximm8,mdata;
  reg write,clk, asel, bsel;
  reg [2:0] vsel, writenum, readnum;
  reg [1:0] ALUop, shift;
  reg loada,loadb,loadc,loads;
  wire [15:0] datapath_out;
  wire N_out,V_out,Z_out;
  
  reg busy;
  
                 
  datapath datapath_tb(.writenum(writenum), .write(write), 
                       .readnum(readnum), .clk(clk), .vsel(vsel), .asel(asel), .bsel(bsel),
                       .shift(shift), .ALUop(ALUop), .loada(loada), .loadb(loadb), 
                       .loadc(loadc), .loads(loads), .datapath_out(datapath_out), .N_out(N_out), 
                       .V_out(V_out), .Z_out(Z_out), .sximm5(sximm5), .sximm8(sximm8), .mdata(mdata));
  initial begin
      sximm5 = 16'b0;
      sximm8 = 16'b0;
      mdata = 16'b0;
  end
  initial begin
      clk = 0;
      repeat(500) #5
      begin
        clk <= ~clk;
      end
  end
  initial begin
    busy = 1;
    //MOV R0, #7
    datapath_in = 16'd7; vsel = 1'b1; write = 1'b1; writenum = 3'd0;
    #10;
    //MOV R1, #2
    datapath_in = 16'd2; vsel = 1'b1; write = 1'b1; writenum = 3'd1;
    #10;
    //ADD R5=9, R1=2, R0=7 
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd1; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd0; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b00; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loadc = 1'b1;
    #10;
    loadc = 1'b0; vsel = 1'b0; write = 1'b1; writenum = 3'd5;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //ADD R2=16=0x10, R1, R0, LSL#1 ;R2 = R1 + (R0 shifted left by 1) = 2+14=16
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd1; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd0; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b00; asel = 1'b0; bsel = 1'b0; shift = 2'b01; 
    loadc = 1'b1;
    #10;
    loadc = 1'b0; vsel = 1'b0; write = 1'b1; writenum = 3'd2;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //MOV R3=2, #2
    datapath_in = 16'd2; vsel = 1'b1; write = 1'b1; writenum = 3'd3;
    #10;
    //CMP R3=2, R1=2 ; zout=1
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd3; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd1; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b01; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loads = 1'b1;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //CMP R216, R1=2; zout=0
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd2; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd1; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b01; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loads = 1'b1;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //CMP R3=2, R1=2;  zout=1
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd3; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd1; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b01; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loads = 1'b1;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //AND R4, R1=2, R0=7
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd1; loada = 1'b1; 
    #10;
    loada = 1'b0; readnum = 3'd0; loadb = 1'b1;
    #10;
    loadb = 1'b0; ALUop = 2'b10; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loadc = 1'b1;
    #10;
    loadc = 1'b0; vsel = 1'b0; write = 1'b1; writenum = 3'd4;
    #10;
    busy = 0;
    #50;
    busy = 1;
    //MVN R6=15, R1=2
    write = 1'b0;//����ֹͣд��, Ҳ���Բ�ֹͣд��
    readnum = 3'd1; loadb = 1'b1; 
    #10;
    loadb = 1'b0; 
    #10;
    loadb = 1'b0; ALUop = 2'b11; asel = 1'b0; bsel = 1'b0; shift = 2'b00; 
    loadc = 1'b1;
    #10;
    loadc = 1'b0; vsel = 1'b0; write = 1'b1; writenum = 3'd6;
    #10;
    busy = 0;
    #50;
    $stop;
  end
endmodule
